Processor architectures with over a hundred cores have been provided since the semiconductor manufacturing process of integrated circuits entered the deep sub-micron (DSM) era. Each of the many cores of a processor architecture is a fully functional processor. Such a processor architecture with many cores is referred to as a manycore system.
The advancement of semiconductor manufacturing process makes integration possible but also brings problems in system yield and reliability. The decrease of yield and system instability caused by signal integrity are very serious on the DSM level. The conventional bus architecture cannot deal with today's huge data flow due to its limitation in scalability, efficiency, and power. Thus, the networks-on-chip (NoC) architecture has become today's standard manycore connection architecture.
In a manycore system, each core works independently or multiple cores work together on a relatively more complicated job. In order to coordinate with each other, the cores need to transmit signals to each other. Accordingly, signal routing is required. FIG. 1 is a schematic diagram of a conventional manycore NoC 100, wherein the circles marked with P are processors, and the squares marked with R are routers. The manycore NoC 100 includes sixteen processors and sixteen corresponding routers. The routers are connected with each other to form a 4×4 matrix, and the processors are respectively connected to the corresponding routers. The processors transmit signals to each other through the routers, and the routers perform signal routing among the processors.
A router may be damaged, and a connection channel between a router and a processor may also be damaged. For example, as shown in FIG. 2, the routers 112 and 132 are damaged, and the connection channel 123 between the router 122 and the processor 121 and the connection channel 143 between the router 142 and the processor 141 are also damaged.
Foregoing damaged routers and connection channels may cause many problems. For example, a normal processor may be isolated by damaged routers and connection channels. As shown in FIG. 2, the processors 111, 121, 131, and 141 are not damaged, but they are isolated respectively by the damaged routers 112 and 132 and the damaged connection channels 123 and 143 therefore cannot contact other processors of the same network. If there are too many damaged routers, an entire network may even be separated into individual areas. For example, as shown in FIG. 3, because the routers 114, 122, 132, and 144 are all damaged, the manycore NoC 100 are separated into two individual areas 310 and 320. The processors of the area 310 cannot contact the processors of the area 320, and vice versa.
Thereby, how to provide a reliable NoC has become one of the major subjects in the industry.
In some conventional manycore NoCs, the microarchitectural redundancy of routers is adopted for reducing the damage rate of the routers. However, such a technique becomes not so cost-effective along with the increase in the number of processors.